A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Nonlinear switched-current CMOS IC for random signal generation

A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6µm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to ~30% of the clock frequency, for a clock frequency of 500kHz

A low-power reconfigurable ADC for biomedical sensor interfaces

This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm. The ADC can be tuned to handle a large variety of biopotential signals, with digitally selectable resolution and input signal amplitude. It achieves 10.4-bit of effective resolution sampling at 56kS/s, with a power consumption below 3μW from a 1V voltage supply.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

A Tool for automated design of sigma-delta modulators using statistical optimization

A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ratio) calculates first optimum specifications for the building blocks (op-amps, comparator, etc.), and then, optimum sizes for their schematics. At both design levels (high-level synthesis and cell dimensioning), optimization is performed via using statistical techniques and innovative heuristics, which allow global design (independent on the initial conditions) and increased computer efficiency as compared to conventional statistical optimization techniques. The tool has been conceived to be flexible at the high-level part(via the use of an architecture independent, behaviourable modeling approach) and completely open at the cell-design part. Performance of the tool is demonstrated via the automatic design of a 16bit-dynamic range, 8Khz second-order SC σδ modulator in 1.2 μm CMOS technology, for which measurements on a fabricated prototype are reported

Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design

This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer of charge in a SC integrator and use power expansion and nonlinear fitting to obtain analytical models to represent harmonic distortion as function of the opamp finite gain-bandwidth (GB), slew-rate (SR) and nonlinear DC gain. Calculated models apply for all modulator architectures where harmonic distortion is dominated by the first integrator in the chain. We show that results provided by the new analytical models fit well to that obtained by simulation in time domain and have accuracy levels much larger than that provided by previously reported modeling approaches

Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors

This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required.Comisión Interministerial de Ciencia y Tecnología TIC97-058

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology

A CMOS fully-differential bandpass ΣΔ modulator using switched-current circuits

This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0.8μm CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation to a second-order lowpass ΣΔ modulator. Specifications are SNR [email protected]±15Khz, for a clock frequency of 1OMhz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5Mhz clock frequency

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔM topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography

Generation of technology-portable flexible analog blocks

This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even to different technology processes. By careful integration of the tuning process of design parameters with layout generation, fully functional designs are generated in a few minutes of CPU time.Ministerio de Ciencia y Tecnología TIC 2001-092